1. Field of the Invention
The invention relates to a semiconductor fabrication process and, more specifically, to a method and system for controlling a semiconductor fabrication process.
2. Description of the Related Art
Semiconductor fabrication process is used for fabricating integrated circuits on silicon wafers using methods known in the art, like, for example, lithography. When fabricating transistors at a nano level (for example, in the sub 0.13-micron region), transistor parameters tend to vary due to variation in the control of various substrate processing steps, such as sub-wavelength lithography and Chemical Mechanical Planarization (CMP) process. As a result, there may be variation in the performance of the fabricated integrated circuit from a desired circuit performance.
A feed-forward methodology often times is used for minimizing such effects of process excursions during the semiconductor fabrication process. The feed-forward methodology generally refers to a method of adjusting succeeding steps in the semiconductor fabrication process based on the process-data of preceding steps of the semiconductor fabrication process.
Conventionally, an advance process control (APC) applies the feed-forward methodologies only to steps that effect transistor formation in the semiconductor fabrication process. For example, process-data collected at the poly cd level is used to correct transistor variance by adjusting succeeding steps for example, etching and/or Lightly Doped Drain (LDD) extension implants. However, relying merely on applying feed-forward method during transistor formation may not provide the best performance of the integrated circuits. Therefore, circuit designers may need to over-design (over-calculate and design accordingly) by looking at a scenario where the transistor performance is worst-case. Moreover, scenarios where metal parasitics also deteriorate the circuit performance may also require the circuit designers to over design.
There is therefore, a need of a method and system for minimizing the effect of process excursion in the semiconductor fabrication process.